一、个人简介

芦宾,1990年3月出生，山西省曲沃县人，汉族，中共党员，副教授，硕士生导师，博士。2013年7月于西安电子科技大学集成电路设计与集成系统专业本科毕业，2013—2019年于西安电子科技大学微电子学与固体电子学专业博士研究生毕业。目前研究方向包括新型半导体器件设计、三值逻辑电路设计、基于深度学习的半导体器件建模及EDA工具开发等。

二、研究课题

  1.山西省基础研究计划，面上，202403021211225，互补三值逻辑反相器设计方法研究，2024-07至2027-07，6万元，主持。

  2.大学生创新创业训练计划项目，重点（国家级大创项目），20220291，基于TGAM脑电在线监测数据的GUI设计，项目成员：刘满意、吴雅娟、程相杨，指导老师：芦宾。

  3.国家自然科学基金，青年科学基金项目，62004119，纳米线环栅隧穿晶体管原理及非准静态模型研究，2021-01至2023-12，24万元，主持。

  4.山西省应用基础研究计划，青年科技研究基金，201901D211400，新型InAs/GaSb 2D-3D量子阱隧穿晶体管，2019-09至2022-09，3万元，主持。

三、出版著作

无

四、发表论文

[1]Lu Bin, Qiang Hua, Liu Xiaotao, Wang Dawei, Cui Yan, Li Zhu, Sun Jiale, Lu Hongliang. Demonstration of a Ternary Inverter Based on the Novel TDDFET With Dual-Doped Source and Asymmetric Gates[J]. IEEE Transactions on Nanotechnology, 2025, 24: 59-66.

[2]Qiang Hua, Lu Haoran, Liu Xiaotao, Xing Linlin, Lu Bin*. Ternary Logic Units Design Based on the TDDFETs[C]. 2024 IEEE 17th International Conference on Solid-State & Integrated Circuit Technology (ICSICT), IEEE, Zhuhai, China, 22-25 October 2024: 1-3.

[3]Lu Bin, Ma Xin, Wang Dawei, Chai Guoqiang, Chen Yulei, Li Zhu, Dong Linpeng. A Ternary Inverter Based on Hybrid Conduction Mechanism of Band-to-Band Tunneling and Drift-Diffusion Process[J]. Micromachines, 2024.04, 15(4): 522.

[4]Lu Bin, Liu Xiaotao, Li Zhu, Di Jiayu, Wang Dawei, Chen Yulei, Doing Linpeng, Miao Yuanhao. A novel nanosheet reconfigurable field effect transistor with dual-doped source/drain[J]. Microelectronics Journal, 2024.05, 147: 106178.

[5]Lu Bin, Wang Dawei, Chai Guoqiang, Chen Yulei, Li Zhu, Sun Jiale, Lu Hongliang. A complementary ternary inverter based on the line tunneling field effect transistors[J]. Microelectronics Journal, 2024.03, 145: 106119.

[6]马鑫, 芦宾*, 董林鹏, 苗渊浩，基于混合导电机制的新型TMOSFET三值逻辑反相器(A novel TMOSFET ternary inverter based on hybrid conduction mechanism) [J]. 物理学报(Acta Physica Sinica). 2023, 72(18): 188501.

[7]Lu Bin, Ma Xin, Wang Dawei, Chai Guoqiang, Dong Linpeng, Miao Yuanhao. A non-quasi-static model for nanowire gate-all-around tunneling field-effect transistors[J]. Chinese Physics B, 2023, 32 (6): 068501.

[8]糜昊, 马鑫, 苗渊浩, 芦宾*, 新型锗源环栅线隧穿晶体管结构设计及优化(Design and Optimization of the Novel Gate⁃all⁃around Line Tunneling FETs with Germanium Source) [J]. 固体电子学研究与进展(RESEARCH & PROGRESS OF SSE), 2022.12, 42(06):441-448.

[9]Lu Bin, Wang Dawei, Cui Yan, Li Zhu, Chai Guoqiang, Dong Linpeng, Zhou jiuren, Wang Guilei, Miao Yuanhao, Lv Zhijun, Lu Honglaing. A Compact Model for Nanowire Tunneling-FETs[J]. IEEE Transactions on Electron Devices, 2022.01, 69(1): 419-426.

[10]芦宾, 王大为, 陈宇雷, 崔艳, 苗渊浩, 董林鹏, 纳米线环栅隧穿场效应晶体管的电容模型(Capacitance model for nanowire gate-all-around tunneling field-effect-transistors) [J]. 物理学报(Acta Physica Sinica). 2021.11, 70(21): 218501.

[11]Lu Bin, Cui Yan, Guo Aixin, Wang Dawei, Lv Zhijun, Zhou Jjiuren, Miao Yuanhao. Characteristics of InAs/GaSb Line-Tunneling FETs With Buried Drain Technique[J]. IEEE Transactions on Electron Devices, 2021.04, 68(4): 1537–1541.

[12]Yang Shizheng, Lv Hongliang*, Lu Bin*, Yan Silu, Zhang Yuming. A Novel Planar Architecture for Heterojunction TFETs With Improved Performance and Its Digital Application as an Inverter[J]. IEEE Access, 2020.01, 8: 23559–23567.

[13]Lu Bin, Lv Zhijun, Lu Hongliang, Cui Yan. A Non-Quasi-Static Model for Tunneling FETs Based on the Relaxation Time Approximation[J]. IEEE Electron Device Letters, 2019.12, 40(12): 1996-1999.

[14]Lu Hongliang*, Lu Bin*, Zhang Yuming, Zhang Yimen, Lv Zhijun. Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture[J]. Nanomaterials, 2019.02, 9(2): 181.

[15]Lu Bin, Lu Honglaing, Zhang Yuming, Zhang Yimen, Lv Zhijun, Zhao Yingxiang. A Novel Planar InAs/Si Hetero-TFET with Buried Drain Design and Face-tunneling Technique[C]. 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, Qingdao, China, 31 Oct.-3 Nov. 2018: 1-3.

[16]Lu Bin, Lu Hongliang, Zhang Yuming, Zhang Yimen, Cui Xiaoran, Lv Zhijun, Liu Chen. Fully Analytical Carrier-Based Charge and Capacitance Model for Hetero-Gate-Dielectric Tunneling Field-Effect Transistors[J]. IEEE Transactions on Electron Devices, 2018.08, 65(8): 3555-3561.

[17]Lu Bin, Lu Hongliang, Zhang Yuming, Zhang Yimen, Cui Xiaoran, Lv Zhijun, Yang Shizheng, Liu Chen. A Charge-Based Capacitance Model for Double-Gate Tunnel FETs With Closed-Form Solution[J]. IEEE Transactions on Electron Devices, 2018.01, 65(1): 299-307.

[18]Lu Bin, Lu Hongliang, Zhang Yuming, Zhang Yimen, Cui Xiaoran, Jin Chengji, Liu Chen. Improved analytical model of surface potential with modified boundary conditions for double gate tunnel FETs[J]. Microelectronics Reliability, 2017.12, 79: 231-238.

[19]Lu Bin, Lv Hongliang, Zhang Yuming, Zhang Yimen, Liu Chen. Comparison of HfAlO, HfO2/Al2O3, and HfO2 on n-type GaAs using atomic layer deposition[J]. Superlattices and Microstructures, 2016.11, 99: 54-57.

五、讲授课程

《电路分析》《数字逻辑》等。

六、获奖情况

  1.2023年山西师范大学“优秀共产党员”称号。